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@ -106,35 +106,35 @@
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</article>
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</article>
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<article>
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<article>
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<a href="projet_pro-fpga.html" class="image featured"><img src="images/FPGA_DE2-70.jpg" alt="Traitement images sur FPGA" /></a>
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<a href="projet_pro-openwide_smile.html#G9MINI" class="image featured"><img src="images/canal_plus.jpg" alt="Canal+: Intégrateur Yocto" /></a>
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<header>
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<header>
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<h3><a href="projet_pro-fpga.html">Traitement images sur FPGA</a></h3>
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<h3><a href="projet_pro-openwide_smile.html#G9MINI">Canal+: Intégrateur Yocto</a></h3>
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</header>
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</header>
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<p>FPGA – VHDL – Profilométrie – Matlab — Algorithme</p>
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<p>Intégration — Yocto — BSP — Linux — SetTopBox</p>
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</article>
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</article>
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<article>
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<article>
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<a href="#" class="image featured"><img src="images/Xvisor.jpg" alt="IRT-systemX: Xvisor" /></a>
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<a href="projet_pro-openwide_smile.html#XVISOR" class="image featured"><img src="images/Xvisor.jpg" alt="IRT-systemX: Xvisor" /></a>
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<header>
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<header>
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<h3><a href="#">IRT-systemX: Xvisor</a></h3>
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<h3><a href="projet_pro-openwide_smile.html#XVISOR">IRT-systemX: Xvisor</a></h3>
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</header>
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</header>
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<p>Noyau Linux — Noyau XVisor — Pilotes I2C — Émulateur — Virtio</p>
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<p>Noyau Linux — Noyau XVisor — Pilotes I2C — Émulateur — Virtio</p>
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</article>
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</article>
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<article>
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<article>
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<a href="#" class="image featured"><img src="images/quantaflow.jpg" alt="Quantaflow: Quantium v2" /></a>
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<a href="projet_pro-openwide_smile.html#QUANTIUM" class="image featured"><img src="images/quantaflow.jpg" alt="Quantaflow: Quantium v2" /></a>
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<header>
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<header>
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<h3><a href="#">Quantaflow: Quantium v2</a></h3>
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<h3><a href="projet_pro-openwide_smile.html#QUANTIUM">Quantaflow: Quantium v2</a></h3>
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</header>
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</header>
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<p>Noyau Linux — Uboot — Buildroot — MTD — Software Update</p>
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<p>Noyau Linux — Uboot — Buildroot — MTD — Software Update</p>
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</article>
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</article>
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<article>
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<article>
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<a href="#" class="image featured"><img src="images/canal_plus.jpg" alt="Canal+: Intégrateur Yocto" /></a>
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<a href="projet_pro-fpga.html" class="image featured"><img src="images/FPGA_DE2-70.jpg" alt="Traitement images sur FPGA" /></a>
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<header>
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<header>
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<h3><a href="#">Canal+: Intégrateur Yocto</a></h3>
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<h3><a href="projet_pro-fpga.html">Traitement images sur FPGA</a></h3>
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</header>
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</header>
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<p>Intégration — Yocto — BSP — Linux — SetTopBox</p>
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<p>FPGA – VHDL – Profilométrie – Matlab — Algorithme</p>
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</article>
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</article>
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<article>
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<article>
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@ -170,9 +170,9 @@
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</article>
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</article>
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<article>
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<article>
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<a href="#" class="image featured"><img src="images/hutchinson.jpg" alt="Hutchinson: AVAC" /></a>
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<a href="projet_pro-openwide_smile.html#AVAC" class="image featured"><img src="images/hutchinson.jpg" alt="Hutchinson: AVAC" /></a>
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<header>
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<header>
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<h3><a href="#">Hutchinson: AVAC</a></h3>
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<h3><a href="projet_pro-openwide_smile.html#AVAC">Hutchinson: AVAC</a></h3>
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</header>
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</header>
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<p>CodeWarrior — Jtag — MPC4604B — C — CAN</p>
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<p>CodeWarrior — Jtag — MPC4604B — C — CAN</p>
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</article>
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</article>
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@ -188,8 +188,8 @@
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<h2>Investissement administratif</h2>
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<h2>Investissement administratif</h2>
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</header>
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</header>
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<p>
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<p>
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| Élus <strong>Délégué du Personnel</strong> chez Smile (2017-20XX).
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| Élus <strong>Délégué du Personnel</strong> chez Smile (2017-20XX).<br />
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| Élus au <strong>Conseil des Études et de la Vie Universitaire</strong> (CEVU) (2012-2014).<br />
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| Élus au <strong>Conseil des Études et de la Vie Universitaire</strong> (CEVU) (2012-2014).
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</p>
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</p>
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</article>
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</article>
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